This invention relates to a structure and a method for providing electrical isolation between active elements, such as nonvolatile or other-type memory cells, in an integrated circuit array. More particularly, this invention relates to isolating such active elements through use of a self-aligned field-plate conductor.
Electrical isolation between the channel regions of active elements, such as transistors in adjacent rows of a memory cell array, has been provided by a variety of methods. Electrical isolation regions include, for example, those regions of the semiconductor substrate surface bounded on two opposite sides by channel regions of field-effect transistors in adjacent rows of a memory array and bounded on the other two sides by buried extensions of the source and drain regions in a column of that array.
One previous method of forming isolation regions has been by junction isolation. Junction isolation regions are implanted with a dopant of the same conductivity type as that of the semiconductor substrate. The higher-level doping in the isolation regions reduces the encroachment of depletion layers of reverse-biased diode junctions into the isolation regions. The source/drain implant extensions are formed by doping the substrate with an impurity of opposite conductivity type. A disadvantage of this type of electrical isolation is the relatively high capacitance formed by the reverse-biased junction, which adversely affects speed of operation of the memory array. Another disadvantage is the inability to downscale the size of the isolation region as the density of the memory cells is increased, while at the same time maintaining the same values for operating voltages.
Another previous method for providing electrical isolation has been the use of thermally-grown field-oxide regions. Field-oxide isolation regions are typically formed by implanting the semiconductor substrate surface with an impurity of the same conductivity type as that of substrate, then exposing the surface to steam at high temperature for a relatively long period of time. During the exposure to steam, thick oxide regions form with lower surfaces below the original surface of the substrate and with upper surfaces above that original surface. One of the disadvantages of this type of isolation is that the edges of the thick oxide regions expand into the surrounding regions, such as adjacent channel regions, using space that might otherwise be used for components.
A third previous method for providing electrical isolation has been the use of trenches etched into the substrate regions, with a light junction isolation doping at the bottom surface and vertical surfaces of the trenches. One of the disadvantages of using trench isolation is the difficulty in filling the trenches with an insulator material that provides a planar surface for later formation of metal or other conductors on the memory chip.
Methods using a field-plate conductor for isolating dynamic random access memory cells are described in U.S. Pat. Nos. 4,696,092 and 4,561,170, also assigned to Texas Instruments Incorporated.
It is desirable to provide a structure and method for electrically isolating active elements, such as transistors in a memory cell array, in a manner that results in decreased bitline capacitance, in a manner that allows dimensions to be down-scaled, in a manner that does not encroach on active surface areas, and in a manner that results in a surface structure better suited for later process steps. In particular, it is desirable to provide a structure and method that permits a reduction in the spacing between rows and/or columns of memory cells, but with no increase in bitline capacitance.